Reasearch Project CONVERS
In order to design systems efficiently, the correct and safe functioning of the entire system has to be ensured as early as possible in the design phase. In addition it is necessary to consider both, analog and digital system behavior. A particular challenge here is the efficient generation of not pure random inputs for the system using so-called constraints. Constraints allow to automatically generate a lot of application scenarios which can be tested. In the project, new methods are developed that allow the use of constraints in the context of the Universal Verification Methodolgy (UVM) to verify mixed analog-digital systems.
Duration of the Project: Jun 1, 2017 - May 31, 2020
Partners: DFKI - German Reasearch Center for Artificial Intelligence & COSEDA Technologies GmbH
In the domain of automotive electronics (e.g. driver assistance systems, autonomous driving), industrial automation, medical technology and Internet-of-Things, a tremendous increase in the complexity of the overall system can be observed. In addition, these systems consist of both analog and digital components (Analog Mixed Signal, AMS). In the development of the next-generation AMS systems, Virtual Prototypes (VPs) are increasingly used. Essentially, a VP is a simulation model of the system to be created in form of a computer program. This model represents the starting point of the system development. However, the development time of a system is increasingly dominated by verification, i.e., to check whether the system behaves according to its specification.
Goal of the Project
DFKI is therefore researching and developing new automated verification methods based on Constrained Random Verification (CRV). These methods represent the state of the art for digital systems. The new methods allow the project partner COSEDA Technologies GmbH to extend the design environment COSIDE to a verification tool. The new verification methods are developed in accordance to the Universal Verification Methodology (UVM).
Publications within the Project
2018
Testbench Qualification for SystemC AMS Timed Data Flow Models
Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler Design, Automation & Test in Europe, o.A., 2018.
2017
Early SoC Security Validation by VP-based Static Information Flow Analysis
Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler IEEE/ACM International Conference on Computer-Aided Design, o.A., 2017. Verifying Next
Generation Electronic Systems
Rolf Drechsler, Daniel Große
International Conference on Infocom Technologies and Unmanned Systems, o.A., 2017.