pll
Project Library Model Name Kind
pll libpll pll Hierarchical Module

Description

hierarchic symbol

Schematic

clk_ref clk_div up dn i_psd1 PSD up dn vcp ictrl i_cp1 ts = 40e-12 vdd = 3.3 current_up = 100e-6 current_dn = 100e-6 current_leak = 50e-9 mosfet_vth = 0.7 CP ictrl vctrl i_lfilter1 c1 = 16e-12 r2 = 115e3 c2 = 300e-12 LFILTER vctrl fout freq i_vco1 tstep = 40e-12 vdd = 3.3 vcm = 1.65 kvo = 36.363636e6 fmin = 2.39e9 VCO fout fin i_div1 n = 2450 vcm = 1.65 DIV clk_o i_clock_src_sc1 <bool> high_level = {T}(1) low_level = {T}(0) period = sca_time(1e-6, SC_SEC) start_time = sc_core::SC_ZERO_TIME duty_cycle = 0.5 CLOCK_SRC_SC t high_level low_level ictrl vctrl fout fdiv fout_freq fin up dn