div_tb
Project Library Model Name Kind
pll libpll div_tb Hierarchical Module

Parameters

Name Type Default Description
fin double 1e3 Input frequency
n long 2 Division ration
vpeak double 3.3 Maximum voltage
vcm double 1.65 Common mode voltage

Description

Frequency divider test bench

Schematic

fout fin i_div n = p.n vcm = p.vcm DIV tdf_o i_sin_src_tdf <double> ampl = p.vcm freq = p.fin offset = p.vcm phase = 0.0 delay = sc_core::SC_ZERO_TIME delta = 0.0 ac_ampl = 1.0 ac_phase = 0.0 sampling_time = sca_time(100e-6, SC_SEC) SIN_SRC_TDF A t fin = 1e3 n = 2 vpeak = 3.3 vcm = 1.65 fin fout
@copyright COSEDA Technologies GmbH. All rights reserved.
(customizable in sca_modules.dtd)