div
Project Library Model Name Kind
pll libpll div Hierarchical Module

Parameters

Name Type Default Description
n long 1 Division ratio
vcm double 0 Common mode voltage to detect edges in the input frequency

Ports

Name Interface Type Description
fout sc_core::sc_out bool output divided frequency
fin sca_tdf::sca_in double input frequency

Description

Frequency divider

Schematic

tdf0_i tdf1_i tdf_o i_cmp_gt_eq_tdf <double,bool> i_const_src_tdf <double> const_val = p.vcm sampling_time = sc_core::SC_ZERO_TIME CONST_SRC_TDF<T> fin IN tdf_i sc_o <bool, bool> i_conv_tdf2de initial_value = {T2}{} <T2> <T1> TDF DE CONV_TDF2DE clk out i_counter n = p.n COUNTER fout OUT n = 1 vcm = 0 vcm_const clk_tdf clk_de
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(customizable in sca_modules.dtd)