std_clock_sc
Project Library Model Name Kind
sca_basic_libraries sources_sc std_clock_sc SystemC Module

Parameters

Name Type Default Description
period sc_core::sc_time sc_core::SC_ZERO_TIME clock period in absolute time units
duty_cycle double 0.5 duty cycle (e.g. 0.5 = 50%)
start_time sc_core::sc_time sc_core::SC_ZERO_TIME time of the first clock edge
posedge_first bool true is the first edge a positiv edge?

Ports

Name Interface Type Description
clk_o sc_core::sc_export sc_core::sc_signal_inout_if<bool> boolean clock output

Description

clock source

Long Description

Discrete event module of a std. SystemC sc_core::sc_clock source with an boolean outport.

The parameter period (default: sc_core::SC_ZERO_TIME) specifies the clock period of the clock generator. The parameter duty_cycle specifies the duty cycle for the clock in the range from 0.0 (always false - 0%) to 1.0 (always true 100%), default is 0.5 (50%). The parameter start_time specifies the time when the clock starts toggling and posedge_first if raising (default: true) or falling edge (false) is the first occured event.

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